1. Field of the Invention
The present invention relates to the management of the program-visible machine state of computers, and more particularly, to a computer register file system and method adapted to handle exceptions which prematurely overwrite register file contents.
2. Related Art
A more detailed description of some of the basic concepts discussed in this application is found in a number of references, including Mike Johnson, Superscalar Microprocessor Design (Prentice-Hall, Inc., Englewood Cliffs, N.J., 1991); John L. Hennessy et al., Computer Architecture—A Quantitative Approach (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., 1990). Johnson's text, particularly Chapter 5, provides an excellent discussion of register file exception handling.
Supporting exception handling and in particular precise interrupts, presents a complicated set of problems for the computer architect. For example, the result of a particular instruction cannot be written to a central processor unit's (CPU) register file, or any other part of the program-visible machine state, until after it can be determined that the instruction will not signal any exceptions. Otherwise, the instruction will have an effect on the visible state of the machine after the exception is signaled. (The terms CPU, computer and processor will be used interchangeably throughout this document).
Historically, this problem has been circumvented by increasing the number of processor pipeline stages (pipeline depth) so that the write does not occur until after the latest exception is determined. However, this reduces the allowable degree of instruction interlocking and/or increases the amount of bypass circuitry required, either of which typically degrades overall performance.
The concept of a “history buffer” is described by J. E. Smith et al. (“Implementation of Precise Interrupts in Pipelined Processors”, Proceedings of the 12th Annual International Symposium on Computer Architecture (Jun. 1985), pp. 36-44), as a means for implementing precise interrupts in a pipeline scalar processor with out-of-order completion. In this approach, the register file contains the program-visible state of the machine, and the history buffer stores items of the in-order state which have been superseded by items of lookahead state (i.e., it contains old values that have been replaced by new values; hence the name history buffer).
The history buffer is managed as a circular buffer. Each entry in the history buffer is assigned an entry number. There are n entries in the history buffer, where n corresponds to the length of the longest functional unit pipeline. A head and a tail tag are used to identify the head of the buffer, and the entry in the buffer reserved for the instruction, respectively. Entries between the head and tail are considered valid.
At issue time, each history buffer entry is loaded with: (1) the value of the register file prior to the issuing of the instruction, and control information including: (2) a destination register of the result, (3) the program counter, and (4) either an exception bit or a validity bit, depending on whether an exception is generated at the time of issue.
A Result Shift Register is used in conjunction with the history buffer to manage various machine control signals, including a reorder tag which is required to properly restore the state of the machine due to out-of-order completion. The result shift register includes entries for the functional unit that will be supplying the result and the destination register of the result. The result shift register is operated as a first-in first-out (FIFO) stack.
Results on a result bus from the processor's functional unit(s) are written directly into the register file when an instruction completes. Exception reports come back as an instruction completes and are written into the history buffer. The exception reports are guided to the proper history buffer entry through the use of tags found in the result shift register. When the history buffer contains an element at the head that is known to have finished without exceptions, the history buffer entry is no longer needed and that buffer location can be re-used (the head pointer is incremented). The history buffer can be shorter than the maximum number of pipeline stages. If all history buffer entries are used (the buffer is too small), issue must be blocked until an entry becomes available. Hence, history buffers are made long enough so that this seldom happens.
When an exception condition arrives at the head of the history buffer, the buffer is held, instruction issue is immediately halted, and there is a wait until pipeline activity completes. The active buffer entries are then emptied from tail to head, and the history values are loaded back into their original registers. The program counter value found in the head of the history is the precise program counter.
The extra hardware required by this method is in the form of a large buffer to contain the history information. Also the register file must have three read ports since the destination value as well as the source operands must be read at issue time.
In view of the forgoing, it is clear that a simplified backup system is therefore required to handle exceptions.